Highly linear low voltage low power CMOS LNA

A highly linear, low voltage, low power, low noise amplifier (LNA) using a novel nonlinearity cancellation technique is presented in this paper. Parallel Inductor (PI) matching is used to increase LNA gain by 3 dB at the desired frequency. The linear LNA was designed and simulated in a TSMC 0.18μm CMOS process at 5GHz frequency. By employing the proposed technique, the IIP3 is improved by 12 dB in contrast to the conventional folded cascode LNA, reaching 1 dBm without having any significant effect on the other LNA parameters such as gain, NF and also power consumption. The proposed LNA also delivers a voltage gain (S21) of 12.25 dB with a noise figure of 3.5 dB, while consuming only 1.28mW of DC power with a low supply voltage of 0.6V.